RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

https://www.rfsocbook.com/ https://www.zynqbook.com/ https://www.zynq-mpsoc-book.com/ SystemVerilog for Verification by Chris Spear Comprehensive Functional Verification: The Complete Industry Cycle Book Next Level Testbenches: Design Patterns in SystemVerilog and UVM by Mark Glasser RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design https://verificationacademy.com/ https://cluelogic.com/2011/07/uvm-tutorial-for-candy-lovers-overview/ UVM Primer and FPGA simulation by Ray Salemi UVM Primer companion videos

I don't know of any video lectures, but I do recommend this book: https://www.amazon.com/RTL-Modeling-SystemVerilog-Simulation-Synthesis/dp/1546776346/